1. Technical Field
The present invention generally relates to signal synchronization between clock domains of Integrated Circuits.
It finds applications, in particular, while not exclusively, in System-On-a Chip Integrated Circuits having a plurality of different clock domains.
2. Related Art
The approaches described in this section could be pursued, but are not necessarily approaches that have been previously conceived or pursued. Therefore, unless otherwise indicated herein, the approaches described in this section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section.
Modem System-On-a-Chip (SOC) Integrated Circuits (ICs) currently include several clock domains and thus are asynchronous systems from the perspective of one clock domain to the others. Signals that are exchanged between different clock domains are crossing boundaries between a source clock domain and a destination source domain, and are thus asynchronously transmitted.
Such signals need to be resynchronized in order to resolve errors which may result from sampling incoming signals in a setup or hold window of flip-flops comprised in the SOC IC.
Synchronization is currently performed in synchronizers containing a fixed number of flip-flops that are serially connected.
The number of flip-flops is determined by a number of parameters, such as clock frequency of the source and destination domains, operating voltage or recovery time of used flip-flops. The number of needed flip-flops is generally computed according to the worst use case, thus leading to an important number of serial flip-flops to support all the possible cases. Indeed, in case of occurrence of an asynchronous event such as, for instance a resetting order, the recovery time of a flip-flop depends on the supply voltage. The recovery time increases when the supply voltage decreases. To enable the flip-flops to more promptly recover synchronization, the number of flip-flops in the synchronizer has to be increased (up to two or three times the original number) for a given sampling rate per synchronizer when the supply voltage is decreasing and if the running frequency is adjusted to the maximum possible one.
However, increasing the number of flip-flops quickly becomes unacceptable in terms of power consumption and die area. Moreover, this strategy is also leading to very long synchronization latency, even when a smaller number of clock delay elements are needed for operation in other conditions.
Thus, there is a need to perform synchronization in asynchronous systems, while ensuring a low power and die area consumption.